Method for mechanical stress enhancement in semiconductor devices

ABSTRACT

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.

PRIORITY DATA

This application claims priority to Provisional Application Ser. No.61/093,155 filed on Aug. 29, 2008, entitled “NOVEL PMOS DESIGN FORDEVICE OPTIMIZATION,” and to Provisional Application Ser. No. 61/098,078filed on Sep. 18, 2008, entitled “METHOD FOR MECHANICAL STRESSENHANCEMENT IN SEMICONDUCTOR DEVICES,” the entire disclosures of whichare hereby incorporated by reference.

BACKGROUND

When a semiconductor device such as a metal-oxide-semiconductorfield-effect transistors (MOSFETs) is scaled down through varioustechnology nodes, high k dielectric material and metal are adopted toform a gate stack. In addition, a strained substrate using epitaxysilicon germanium (SiGe) may be used to enhance the carrier mobility.However, there is no strained engineering process correlated to circuitdesign optimization, especially in the epitaxy SiGe feature. Therefore,the epitaxy SiGe feature at an active region edge may cause mismatchissue and device performance degradation. Additionally, in the currentdevice structure, the active region has a profile with a facet shape atthe edge of the active region. The channel stress is decreased and thedevice performance is degraded thereby.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1-2 are top views of two examples of a conventional semiconductorstructure;

FIG. 3 is a top view of a semiconductor structure constructed accordingto aspects of the present disclosure in an embodiment;

FIG. 4 is a top view of a semiconductor structure constructed accordingto aspects of the present disclosure in another embodiment; and

FIGS. 5 through 8 are top views of a semiconductor structure constructedaccording to aspects of the present disclosure in various embodiments.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof various embodiments. Specific examples of components and arrangementsare described below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a first feature over or on a second featurein the description that follows may include embodiments in which thefirst and second features are formed in direct contact, and may alsoinclude embodiments in which additional features may be formedinterposing the first and second features, such that the first andsecond features may not be in direct contact.

FIGS. 1-2 are top views of two examples of an existing semiconductorstructures. In FIG. 1, the semiconductor device 100 includes an activeregion 102 defined in a semiconductor substrate. The active region issurrounded by isolation regions, such as shallow trench isolation (STI)features. The active region 102 has a length L1 as illustrated inFIG. 1. One or more operational devices 104, such as devices 1, 2, . . .and n, are formed in the active region 102. The gate features of devices104 may be extended out from the active region for electric connection.Furthermore, one or more dummy gates 106 are disposed in the isolationregion, adjacent the active region and configured with the operationaldevice array in a similar pitch “P”, as illustrated in FIG. 1. However,this structure suffers non-symmetric source and drain, poor STI-edgeleakage & degraded device performance.

In FIG. 2, the semiconductor device 150 includes an active region 152defined in a semiconductor substrate. The active region 152 issurrounded by isolation regions, such as STI features. The active region152 has a length L2 as illustrated in FIG. 2. One or more operationaldevices 154, such as devices 1, 2, . . . and n, are formed in the activeregion 152. The gate features of devices 154 may be extended out beyondthe active region for electric connection. Furthermore, one or moredummy gates 156 are disposed in the isolation region, adjacent theactive region and configured with the operational device array 154 in asimilar pitch “P”, as illustrated in FIG. 2. However, this structuresuffers dummy polysilicon peeling, poor polysilicon photo depth of focus(DOF), STI-edge leakage and spacer leakage.

FIG. 3 is a top view of a semiconductor structure 200 constructedaccording to aspects of the present disclosure. The semiconductorstructure 200 is described below according to one or more embodiments.The semiconductor device 200 includes an active region 202 defined in asemiconductor substrate (not shown). The semiconductor substrate is asilicon substrate. Various shallow trench isolation (STI) structures areformed in the semiconductor substrate such that various active regionsare determined accordingly. In the example of FIG. 3 for illustration,an active region 202 is defined in the semiconductor substrate andsurrounded by an isolation feature 203. The active region 202 has alength L3 as illustrated in FIG. 3.

One or more operational devices 204, such as devices 1, 2, . . . and n,are formed in the active region 202. The operational devices 204 arefield-effect transistors (FETs). In one example, the FETs aremetal-oxide-semiconductor transistors (MOSFETs). Each MOSFET includes asource and drain regions formed in the semiconductor substrate, a gatestack formed on the semiconductor substrate and horizontally interposedbetween the source and drain regions. A channel defined in the substrateand configured between the source and drain, and underlying the gatestack. The channel is strained to enable the carrier mobility of thedevice and enhance the device performance. Particularly, the source anddrain regions are formed by an epitaxy process with a semiconductordifferent from silicon to achieve the strained channel. In oneembodiment, the silicon germanium (SiGe) is deposited by an epitaxyprocess on the silicon substrate to form the source and drain regions.In furtherance of the embodiment, the FETs are p-type MOSFETs. Thesource and drain regions of the PMOSFETs are made of epi SiGe. Inanother embodiment, the silicon carbide (SiC) is deposited by an epitaxyprocess on the silicon substrate to form the source and drain regions.In furtherance of the embodiment, the FETs are n-type MOSFETs. Thesource and drain regions of the NMOSFETs are made of epi SiC. In anotherembodiment, The FETs includes PMOS with source/drain regions of epi SiGeand NMOS with source/drain regions of epi SiC. In another embodiment,the gate stack includes a high k dielectric material layer disposed onthe substrate, a metal layer disposed on the high k dielectric materiallayer. Additionally, an interfacial layer, such as silicon oxide, may beinterposed between the high k dielectric material layer and the metallayer.

The operational devices 204 are configured as an array in the activeregion 202 as illustrated FIG. 3. The pitch of the device array islabeled as “P” in FIG. 3. In one side of the device array 204, one ormore dummy gate stacks 206 are positioned in the same active region 202and is aligned with the device array with the same pitch to the adjacentdevice of the device array 204. Similarly, in other side of the devicearray 204, one or more dummy gate stacks 206 are positioned in the sameactive region 202 and is aligned with the device array with the samepitch to the adjacent operational device of the device array 204. Thusthe device array 204 within the active region 202 is enclosed by thedummy gate stacks 206. In another words, the device array 204 issandwiched by the dummy gate stacks 206. The dummy gate stacks aresubstantially same to the gate stacks of the operational devices interms of formation, composition and structure.

The disclosed structure addresses the issues noted above and enhancesthe device performance. It is noted that length “L3” of the activeregion in the disclosed semiconductor structure 200 is greater than “L1”of the structure 100 and “L2” of the structure 150 if other parametersare same. As the active region is further extended such that the dummygate is also disposed in the active region instead of the isolationregion, the STI related stress is reduced and the epi source/drainrelated stress is more uniform to the operational devices 204.

One example of the advantages associated with the disclosed structure isprovided. Since the circuit design is aligned with the strainedtransistor engineering process according to the disclosed structure, thecircuit design is improved for PMOS transistor with epi SiGesource/drain regions. Other advantages may present in variousapplications, such as minimizing layout degradation effects (LDE) inPMOS device; resolving non-symmetric SiGe S/D; reducing STI-edge leakageand improving device performance. Additionally, since the circuit designlayout is designed according to the disclosed structure, there is nochange to the fabrication process flow. Therefore, there is noadditional masking cost and wafer manufacturing cost. It is understoodthat different embodiments disclosed herein offer different advantagesand that no particular advantage is necessarily required for allembodiments.

FIG. 4 is a top view of a semiconductor structure (integrated circuit)220 constructed according to aspects of the present disclosure inanother embodiment. The semiconductor structure 220 is described belowaccording to one or more embodiments. The semiconductor device 220includes an active region 202 defined in a semiconductor substrate (notshown). The semiconductor substrate is a silicon substrate. Variousshallow trench isolation structures are formed in the semiconductorsubstrate such that various active regions are determined accordingly.In the example of FIG. 4 for illustration, an active region 202 isdefined in the semiconductor substrate and surrounded by the isolationfeature 203, such as a STI. The active region 202 has a length L4 asillustrated in FIG. 4.

One or more operational devices 204, such as devices 1, 2, . . . and n,are formed in the active region 202. The operational devices 204 areFETs, similar to those illustrated in FIG. 3. Particularly, the channelis strained to enable the carrier mobility of the device and enhance thedevice performance. The source and drain regions are formed by anepitaxy process with a semiconductor different from silicon to achievethe strained channel. In one embodiment, the SiGe is deposited by anepitaxy process on the silicon substrate to form the source and drainregions. In furtherance of the embodiment, the FETs are p-type MOSFETs.The source and drain regions of the PMOSFETs are made of epi SiGe. Inanother embodiment, the SiC is deposited by an epitaxy process on thesilicon substrate to form the source and drain regions. In furtheranceof the embodiment, the FETs are n-type MOSFETs. The source and drainregions of the NMOSFETs are made of epi SiC. In another embodiment, TheFETs includes PMOS with source/drain regions of epi SiGe and NMOS withsource/drain regions of epi SiC. In another embodiment, the gate stackincludes a high k dielectric material layer disposed on the substrate, ametal layer disposed on the high k dielectric material layer.Additionally, an interfacial layer, such as silicon oxide, may beinterposed between the high k dielectric material layer and the metallayer.

The operational devices 204 are configured as an array in the activeregion 202 as illustrated FIG. 4. The pitch of the device array islabeled as “P” in FIG. 4. In one side of the device array 204, one ormore dummy gate stacks 206 are positioned at least partially in the sameactive region 202 and is aligned with the device array 204 with the samepitch to the adjacent operational device of the device array 204.Similarly, in other side of the device array 204, one or more dummy gatestacks 206 are positioned at least partially in the same active region202 and is aligned with the device array 202 with the same pitch to theadjacent operational device of the device array 204. Thus the devicearray 204 within the active region 202 is enclosed by the dummy gatestacks 206. The dummy gate stacks are substantially same to the gatestacks of the operational devices in terms of formation, composition andstructure. In another embodiment, the dummy gates are positioned to bebutted to the edge of the active region 202.

The semiconductor structure 220 further includes one or more dummyactive regions 208 disposed adjacent to the active region 202. Theactive regions and dummy active regions each is separated from theothers by the isolation feature 203, such as a shallow trench isolationstructure. With the dummy active regions, the substrate stress can betuned according to the designed strain effect to the substrate forenhanced mobility. The one or more dummy active regions 208 are disposedsurrounding the active region 202 in a configuration such that theactive regions (including both the dummy active regions and theoperational active regions) have a substantial uniform density on thesubstrate. As another example, the proper configuration of the dummyactive regions can improve the chemical mechanical polishing (CMP)processing effect when a CMP process is applied to the substrate duringthe formation of the STI structures. The dummy active regions 208 mayhave similar dimensions to those of the active region 202 in oneexample. The dummy active regions 208 may be disposed around the activeregion 202 with a proper distance in another example.

One or more additional dummy gates 210 are disposed on the dummy activeregions 208 and may be additionally disposed on the STI. The dummy gatesdisposed on the dummy active regions 208 and on the STI aresubstantially similar to the dummy gates 204 on the active region 202and similar to the operational gates of the devices 204 in terms of theformation, composition and dimension. The dummy gates 206 and 210 areconfigured with the operational devices 204 such that the gate densityon the substrate are substantially uniform, therefore the boundaryeffect of the active region is minimized and the stress built in thesubstrate for the strained substrate is substantially maintained. Thedummy gates 210 are aligned with the device array 204 with the samepitch to the adjacent operational device of the device array 204.

The disclosed semiconductor structure 220 addresses the issues notedabove and enhances the device performance. It is noted that length “L4”of the active region in the disclosed semiconductor structure 220 isgreater than “L1” of the structure 100 if other parameters are same andis greater than “L2” of the structure 150 if the dummy gates are atleast partially on the active region. As the active region is furtherextended such that at least a portion of the dummy gates is alsodisposed in the active region 202, the STI related stress is reduced andthe epi source/drain related stress is more uniform to the operationaldevices 204. Furthermore, the dummy active regions 208 and the dummygates 210 disposed on the dummy active regions and on the STI arefurther configured on the semiconductor structure 220 to address theabove issue and enhance the device performance.

As the furtherance of the semiconductor structure 220 of FIG. 4, variousembodiments are further provided for illustration. FIGS. 5 through 8 aretop views of a semiconductor structure constructed according to aspectsof the present disclosure in various embodiments. FIG. 5 illustrates asemiconductor structure 250 having the active region 202, the dummyactive region 208, the operational gates 204, and the dummy gates 206and 210. In the semiconductor structure 250, the dummy gates 206 arepositioned to be butted to the active region 202. The dummy activeregion 208 is aligned with the active region 202. The dummy activeregion 208 and the dummy gates 210 are configured in a way similar tothe configuration of the active region 202, the dummy gates 206 anddevice 204. Therefore, the semiconductor structure 250 is referred to asa symmetric structure. In this example, only one device 204 isillustrated. One dummy gate 206 is disposed on each side of the device204. However, the illustrated number of the device 204 and number of thedummy gates 206 are only examples and are not mean to be limiting.

FIG. 6 illustrates a semiconductor structure 260 having the activeregion 202, the dummy active regions 208, the operational gates 204, andthe dummy gates 206 and 210. In the semiconductor structure 260, thedummy gates 206 are positioned to be butted to the active region 202.More than one dummy active regions 208 are aligned with the activeregion 202 and each may have an individual dimension. Therefore, thissemiconductor structure 260 is referred to as an asymmetric structure.In one example, the dummy active regions are deigned such that thepattern density of the active regions are substantially uniform. Inanother example, the dummy gates 210 are aligned with the dummy gates206 and device 204 with a same pitch.

FIG. 7 illustrates a semiconductor structure 270 having the activeregion 202, the dummy active region 208, the operational gates 204, andthe dummy gates 206 and 210. In the semiconductor structure 270, thedummy gates 206 are positioned partially on the active region 202. Thedummy active region 208 is aligned with the active region 202.Similarly, the dummy gates 210 are positioned partially on the dummyactive region 208. The dummy active region 208 is aligned with theactive region 202. The dummy active region 208 and the dummy gates 210are configured in a way similar to the configuration of the activeregion 202, the dummy gates 206 and device 204 such that all gates arealigned with a same pitch. Therefore, the semiconductor structure 270 isreferred to as a symmetric structure.

FIG. 8 illustrates a semiconductor structure 280 having the activeregion 202, the dummy active regions 208, the operational gates 204, andthe dummy gates 206 and 210. In the semiconductor structure 280, thedummy gates 206 are positioned partially on the active region 202. Morethan one dummy active regions 208 are aligned with the active region 202and each may have an individual dimension. Therefore, this semiconductorstructure 280 is referred to as an asymmetric structure. In one example,the dummy active regions are designed such that the pattern density ofthe active regions are substantially uniform. In another example, thedummy gates 210 are aligned with the dummy gates 206 device 204 with asame pitch and are partially on the dummy active region. A portion ofthe dummy gates may be positioned on the STI to achieve an uniformpattern density of the gate array (including the operational gates anddummy gates).

Various examples of the advantages associated with the disclosedstructure are provided. Since the circuit design is aligned with thestrained transistor engineering process according to the disclosedstructure, the circuit design is improved for PMOS transistor with epiSiGe source/drain regions. In another example with butted dummy gates(or dummy gates at least partially on the active region) and the dummyactive regions, the facet shape is avoided and the channel stress isincreased. Other advantages may present in various applications, such asminimizing layout degradation effects (LDE) in PMOS device; and reducingSTI-edge leakage and improving device performance. Additionally, sinceonly circuit design layout is designed according to the disclosedstructure, there is no change to the fabrication process flow.Therefore, there is no additional masking cost and manufacturing cost.

Although embodiments of the present disclosure have been described indetail, those skilled in the art should understand that they may makevarious changes, substitutions and alterations herein without departingfrom the spirit and scope of the present disclosure. In one embodiment,various dummy gates are disposed in a seal ring area. Thus the gatelayers are patterned not only in the circuit regions but also in theseal ring regions, achieving an uniform pattern density of the gatelayers in both circuit regions and seal ring regions. The dummy gates inthe seal ring regions can be formed in the same process to form theoperational gates and other dummy gates. In one embodiment, the dummygate density ranges between about 20% and about 40%. Various devicefeatures of the semiconductor structure 200/220 and the method to makethe same are further described below according to more embodiments. Inone example, the semiconductor substrate may alternatively includesother semiconductor material, such as diamond, silicon carbide orgallium arsenic.

In another embodiment, the semiconductor substrate may include anepitaxial layer. For example, the substrate may have an epitaxial layeroverlying a bulk semiconductor. Furthermore, the substrate may include asemiconductor-on-insulator (SOI) structure such as a buried dielectriclayer. Alternatively, the substrate may include a buried dielectriclayer such as a buried oxide (BOX) layer, such as that formed by amethod referred to as separation by implantation of oxygen (SIMOX)technology, wafer bonding, selective epitaxial growth (SEG), or otherproper method.

The formation of STI may include etching a trench in a substrate andfilling the trench by insulator materials such as silicon oxide, siliconnitride, or silicon oxynitride. The filled trench may have a multi-layerstructure such as a thermal oxide liner layer with silicon nitridefilling the trench. In one embodiment, the STI structure may be createdusing a process sequence such as: growing a pad oxide, forming a lowpressure chemical vapor deposition (LPCVD) nitride layer, patterning anSTI opening using photoresist and masking, etching a trench in thesubstrate, optionally growing a thermal oxide trench liner to improvethe trench interface, filling the trench with CVD oxide, using chemicalmechanical planarization (CMP) to etch back, and using nitride strippingto leave the STI structure.

The metal gate stacks for both operational devices and dummy gates aresimilar in terms of composition, dimension, formation and structure.These gate stacks can be formed in a single process. In one embodiment,a high k dielectric material layer is formed on the semiconductorsubstrate. A metal gate layer is formed on the high k dielectricmaterial layer. A capping layer is further interposed between the high kdielectric material layer and the metal gate layer. The high kdielectric material layer is formed by a suitable process such as anatomic layer deposition (ALD). Other methods to form the high kdielectric material layer include metal organic chemical vapordeposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidationand molecular beam epitaxy (MBE). In one embodiment, the high kdielectric material includes HfO2. In another embodiment, the high kdielectric material includes Al2O3. Alternatively, the high k dielectricmaterial layer includes metal nitrides, metal silicates or other metaloxides. The metal gate layer is formed by PVD or other suitable process.The metal gate layer includes titanium nitride. In another embodiment,the metal gate layer includes tantalum nitride, molybdenum nitride ortitanium aluminum nitride. The capping layer is interposed between thehigh k dielectric material layer and the metal gate layer. The cappinglayer includes lanthanum oxide (LaO). The capping layer mayalternatively includes other suitable material.

In another embodiment of the metal gate stack, an interfacial layer,such as silicon oxide, is formed on the substrate before the depositionof the high k dielectric material layer. The silicon oxide may be formedby a thermal oxidation or atomic layer deposition (ALD). The thinsilicon oxide layer is formed on the silicon substrate. A high kdielectric material layer is formed on the silicon oxide layer by ALD orother suitable process. The high k dielectric material includes HfO2 orother suitable material. A capping layer is formed on the high kdielectric material layer. The capping layer includes lanthanum oxide orother suitable material. A metal gate layer is formed on the cappinglayer by PVD or other suitable method. The metal gate layer includestitanium nitride or other proper material as provided above. Apolysilicon layer or a metal layer such as tungsten or aluminum isfurther formed on the metal gate layer by chemical vapor deposition(CVD), plating, physical vapor deposition (PVD) or other suitablemethod. Then the various metal gate stack layers are patterned to formboth operational metal gate stacks and dummy gate stacks.

Then the various gate material layers are patterned to form gate stacksfor both operational devices and the dummy gates. The method to patternthe gate material layers includes applying various dry and wet etchingsteps, using a patterned mask defining various openings. The gate layerswithin the openings of the patterned mask are removed by the one oretching processes. In one embodiment, the first dry etching processutilizes fluorine-containing plasma to remove the polysilicon or themetal gate layer. The patterned mask is formed on the multiplemetal-gate-stack layers. In one example, the patterned mask is apatterned photoresist layer formed by a photolithography process. Anexemplary photolithography process may include processing steps ofphotoresist coating, soft baking, mask aligning, exposing, post-exposurebaking, developing photoresist and hard baking. The photolithographyexposing process may also be implemented or replaced by other propermethods such as maskless photolithography, electron-beam writing,ion-beam writing, and molecular imprint. In another embodiment, thepatterned mask layer includes a patterned hard mask layer. In oneexample, the patterned hard mask layer includes silicon nitride. As oneexample of forming the patterned silicon nitride hard mask, a siliconnitride layer is deposited on the polysilicon layer by a low pressurechemical vapor deposition (LPCVD) process. The silicon nitride layer isfurther patterned using a photolithography process to form a patternedphotoresist layer and an etching process to etch the silicon nitridewithin the openings of the patterned photoresist layer. Alternatively,other dielectric material may be used as the patterned hard mask. Forexample, silicon oxynitride may be used as the hard mask.

Then one or two types epi semiconductor materials can be grew after theformation of the gate stacks, by a selective epi growth (SEG). The episemiconductor layer is self-aligned with source and drain regions. Inone example, SiGe is epi grew in the source and drain regions of thePMOS transistors. In another example, the SiC us epi grew in the sourceand drain regions of the NMOS transistors. The epi formed source anddrain features on the silicon substrate is able to induce the stress tothe associated channel and therefore to tune the carrier mobilitythereof to enhance the device performance.

One or more ion implantation steps are further performed to form variousdoped regions, such as doped sources and drains, and/or light dopeddrain (LDD) features. In one example, the LDD regions are formed afterthe formation of the gate stack and/or the epi source and drain region,and therefore aligned with the gate stacks. A gate spacer may be formedon the sidewalls of the metal gate stack. Then heavy source and draindoping processes are performed to form heavy doped sources and drains,and therefore the heavy doped sources and drains are substantiallyaligned with the outer edges of the spacers. The gate spacers may have amultilayer structure and may include silicon oxide, silicon nitride,silicon oxynitride, or other dielectric material. The doped source anddrain regions and LDD regions of either an n-type dopant or a p-typedopant are formed by a conventional doping process such as ionimplantation. N-type dopant impurities employed to form the associateddoped regions may include phosphorus, arsenic, and/or other materials.P-type dopant impurities may include boron, indium, and/or othermaterials. silicide are formed on the raised source and drain featuresto reduce the contact resistance. Then silicide can be formed on thesources and drains by a process including depositing a metal layer,annealing the metal layer such that the metal layer is able to reactwith silicon to form silicide, and then removing the non-reacted metallayer.

Then an inter-level dielectric (ILD) layer is formed on the substrateand a chemical mechanical polishing (CMP) process is further applied tothe substrate to polish the substrate. In another example, an etch stoplayer (ESL) is formed on top of the gate stacks before forming the ILDlayer. In one embodiment, the gate stacks formed above are final metalgate structure and remain in the final circuit. In another embodiment,the thus formed gate stacks are partially removed and then refilled withproper materials for various fabrication consideration such as thermalbudget. In this case, the CMP process is continued until the polysiliconsurface is exposed. In another embodiment, the CMP process is stopped onthe hard mask layer and then the hard mask is removed by a wet etchingprocess.

A multilayer interconnection (MLI) is formed on the substrate toelectrically connect various device features to form a functionalcircuit. The multilayer interconnection includes vertical interconnects,such as conventional vias or contacts, and horizontal interconnects,such as metal lines. The various interconnection features may implementvarious conductive materials including copper, tungsten and silicide. Inone example, a damascene process is used to form copper relatedmultilayer interconnection structure. In another embodiment, tungsten isused to form tungsten plug in the contact holes.

The semiconductor structure 200 serves only as one example. Thesemiconductor structure 200 may be used in various applications such asdigital circuit, imaging sensor devices, a hetero-semiconductor device,dynamic random access memory (DRAM) cell, a single electron transistor(SET), and/or other microelectronic devices (collectively referred toherein as microelectronic devices). Of course, aspects of the presentdisclosure are also applicable and/or readily adaptable to other type oftransistor, including single-gate transistors, double-gate transistorsand other multiple-gate transistors, and may be employed in manydifferent applications, including sensor cells, memory cells, logiccells, and others.

Although embodiments of the present disclosure have been described indetail, those skilled in the art should understand that they may makevarious changes, substitutions and alterations herein without departingfrom the spirit and scope of the present disclosure. In one embodiment,the disclosed structure is applicable to a p-typemetal-oxide-semiconductor field-effect-transistor (PMOSFET). In anotherembodiment, strained channel and metal gate stack are combined with thedisclosed structure with operational device array and dummy gate in thesame active regions in the way such that the device performance areconsistent and uniform for those operational devices in the same activeregion. In another embodiment, the NMOS transistors, PPMOS transistorsand dummy gate stacks are configured in the same active regions to formcomplementary MOS transistors with optimized device performance.

Thus, the present disclosure provides an integrated circuit. Theintegrated circuit includes an active region in a semiconductorsubstrate; at least one operational device on the active region, whereinthe operational device include a strained channel; and a first dummygate disposed at a side of the operational device and on the activeregion.

The integrated circuit may further include a dummy active region in thesemiconductor substrate and adjacent the active region; a shallow trenchisolation (STI) in the semiconductor substrate and interposed betweenthe active region and the dummy active region; and a second dummy gatedisposed on the dummy active region. The integrated circuit may furtherinclude a third dummy gate disposed at another side of the operationaldevice and on the STI. The first dummy gate may be partially positionedon the active region.

In the disclosed integrated circuit, wherein the first dummy gate ispartially positioned on the active region. In one embodiment, the firstdummy gate is partially positioned on the active region. The integratedcircuit may further include a third dummy gate disposed at another sideof the operational device and on STI. The operational device may includean epi silicon germanium (SiGe). source/drain feature. In this case, theoperational device is a p-type metal-oxide-semiconductor field-effecttransistor (PMOSFET). In another embodiment, the operational device mayinclude an n-type MOSFET (NMOSFET) having a silicon source/drainfeature; and a PMOSFET having an epi SiGe source/drain feature. Inanother embodiment, the operational device may include an NMOSFET havingan epi silicon carbide (SiC) source/drain feature; and a PMOSFET havingan epi SiGe source/drain feature. In another embodiment, the operationaldevice may include an NMOSFET having an epi silicon carbide (SiC)source/drain feature; and a PMOSFET having a silicon source/drainfeature. The operational device may further include a metal gate stackhaving a high k dielectric material layer and a metal layer disposed onthe high k dielectric material layer. The dummy gate may include asecond metal gate stack having the high k dielectric material layer andthe metal layer disposed on the high k dielectric material layer. In oneembodiment, the integrated circuit may further includes a seal ringregion in a semiconductor substrate; and a second dummy gate disposed onthe seal ring region.

The present disclosure also provides another embodiment of an integratedcircuit. The circuit includes a silicon substrate having an activeregion and a dummy active region; a shallow trench isolation interposedbetween the active region and the dummy active region; a plurality ofn-type metal-oxide-semiconductor (NMOS) transistors and a plurality ofPMOS transistors on the active region, wherein the NMOS transistorsinclude a first type source and drain regions made by a firstsemiconductor material and the PMOS transistors include a second typesource and drain region made by a second semiconductor materialdifferent from the first semiconductor material; a first and a seconddummy gates disposed on the STI and enclosing the NMOS and PMOStransistors; and a third dummy gate disposed on the dummy active region.

In the disclosed integrated circuit, one of the first and second dummygate may be butted to an edge of the active region. In anotherembodiment, one of the first and second dummy gate may be partially onthe active region. The first type source and drain regions may includesilicon and the second type source and drain regions include silicongermanium (SiGe). In another embodiment, the first type source and drainregions include silicon carbide (SiC) and the second type source anddrain regions include silicon germanium (SiGe). In another embodiment,the first type source and drain regions include silicon carbide (SiC)and the second type source and drain regions include silicon. In anotherembodiment, the second type source and drain regions are formed by anepitaxy process.

The present disclosure also provides another embodiment of an integratedcircuit. The circuit includes a silicon substrate having an activeregion and a dummy active region; a shallow trench isolation (STI)formed in the semiconductor substrate, surrounding the active region andinterposed between the active region and the dummy active region; aplurality of field-effect transistors (FETs) on the active region,wherein each of the FETs includes a metal gate stack; source and drainregions made disposed on the sides of the metal gate stack and by an episemiconductor material different from silicon; and a strained channelunderlying the metal gate stack. The circuit further includes a firstdummy metal gate stack disposed on the active region and at a first sideof the FET transistors; a second dummy metal gate stack disposed on theactive region and at a second side of the FET transistors, such that thefirst and second dummy gates enclosing the FETs; and a third dummy gatedisposed on the dummy active region.

In one embodiment of the disclosed integrated circuit, the FETs arep-type metal-oxide-semiconductor FETs (PMOSFETs) and the episemiconductor material includes silicon germanium (SiGe). In anotherembodiment, the FETs are n-type metal-oxide-semiconductor FETs(NMOSFETs) and the epi semiconductor material includes silicon carbide(SiC). The metal gate stack may include a high k dielectric materiallayer and a metal layer disposed on the high k dielectric materiallayer. The metal gate stack may further include a capping layerinterposed between the high k dielectric material layer and the metallayer. One of the first and second dummy metal gate stacks may bepositioned partially on the STI.

The foregoing has outlined features of several embodiments. Thoseskilled in the art should appreciate that they may readily use thepresent disclosure as a basis for designing or modifying other processesand structures for carrying out the same purposes and/or achieving thesame advantages of the embodiments introduced herein. Those skilled inthe art should also realize that such equivalent constructions do notdepart from the spirit and scope of the present disclosure, and thatthey may make various changes, substitutions and alterations hereinwithout departing from the spirit and scope of the present disclosure.

What is claimed is:
 1. An integrated circuit, comprising: an activeregion in a semiconductor substrate; at least one operational device onthe active region, wherein the operational device includes a strainedchannel; a first dummy gate disposed at a side of the operational deviceand directly on the active region; a dummy active region in thesemiconductor substrate and adjacent the active region; a shallow trenchisolation (STI) interposed between the active region and the dummyactive region; and a second dummy gate disposed on the dummy activeregion.
 2. The integrated circuit of claim 1, further comprising a thirddummy gate disposed on the STI.
 3. The integrated circuit of claim 1,wherein the first dummy gate is partially positioned on the activeregion.
 4. The integrated circuit of claim 1, wherein the second dummygate is disposed at another side of the operational device.
 5. Theintegrated circuit of claim 1, wherein the operational device comprisesan epi silicon germanium (SiGe) source/drain feature.
 6. The integratedcircuit of claim 5, wherein the operational device is a p-typemetal-oxide-semiconductor field-effect transistor (PMOSFET).
 7. Theintegrated circuit of claim 1, wherein the operational device comprises:an n-type MOSFET (NMOSFET) having a silicon source/drain feature; and aPMOSFET having an epi SiGe source/drain feature.
 8. The integratedcircuit of claim 1, wherein the operational device comprises: an NMOSFEThaving an epi silicon carbide (SiC) source/drain feature; and a PMOSFEThaving an epi SiGe source/drain feature.
 9. The integrated circuit ofclaim 1, wherein the operational device comprises: an NMOSFET having anepi silicon carbide (SiC) source/drain feature; and a PMOSFET having asilicon source/drain feature.
 10. The integrated circuit of claim 1,wherein the operational device includes a high-k/metal gate stack. 11.The integrated circuit of claim 1, further comprising: a seal ringregion in a semiconductor substrate; and wherein the second dummy gateis disposed on the seal ring region.
 12. The integrated circuit of claim1, wherein the first dummy gate stack is positioned butted to the activeregion.
 13. An integrated circuit, comprising: a silicon substratehaving an active region and a dummy active region; a shallow trenchisolation surrounding the active region and interposed between theactive region and the dummy active region; a plurality of n-typemetal-oxide-semiconductor (NMOS) transistors and a plurality of PMOStransistors on the active region, wherein the NMOS transistors includefirst type source and drain regions made by a first semiconductormaterial and the PMOS transistors include second type source and drainregions made by a second semiconductor material different from the firstsemiconductor material; first and second dummy gates disposed on the STIsuch that the NMOS transistors and the PMOS transistors are located inbetween the first and second dummy gates, wherein one of the first andsecond dummy gates is directly on the active region; and a third dummygate disposed on the dummy active region.
 14. The integrated circuit ofclaim 13, wherein the first dummy gate is butted to an edge of theactive region.
 15. The integrated circuit of claim 13, wherein the firstdummy gate is partially on the active region.
 16. The integrated circuitof claim 13, wherein the first type source and drain regions includesilicon carbide (SiC).
 17. The integrated circuit of claim 13, whereinthe second type source and drain regions include silicon germanium(SiGe).
 18. An integrated circuit, comprising: a semiconductor substratehaving an active region and a dummy active region; a shallow trenchisolation (STI) formed in the semiconductor substrate, surrounding theactive region and interposed between the active region and the dummyactive region; a plurality of field-effect transistors (FETs) on theactive region, wherein each of the FETs includes: a metal gate stack; asource region and a drain region interposed by the metal gate stack,wherein both the source region and the drain region include an episemiconductor material; and a strained channel underlying the metal gatestack; a first dummy metal gate stack disposed directly on the activeregion and at a first side of the FETs; a second dummy metal gate stackdisposed directly on the active region and at a second side of the FETs,such that the first dummy metal gate stack and the second dummy metalgate stack enclose the FETs; and a third dummy metal gate stack disposedon the dummy active region.
 19. The integrated circuit of claim 18,wherein first dummy metal gate stack and the second dummy metal gatestack are each butted to the active region.
 20. The integrated circuitof claim 18, wherein the wherein first dummy metal gate stack and thesecond dummy metal gate stack are each positioned partially on theactive region.